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Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
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机译:使用应变硅锗层的选择性外延的互补金属氧化物半导体晶体管技术
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摘要
A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.
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