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The n channel and the p channel MOS device for the thin epitaxial RESURF integrated circuit null high tension where it includes the HVp channel and the n channel
The n channel and the p channel MOS device for the thin epitaxial RESURF integrated circuit null high tension where it includes the HVp channel and the n channel
N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and of a source or drain region, respectively, of the high voltage complementary MOS devices. The devices may be configured as source or drain followers without problems. IMAGE
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