首页> 外国专利> CIRCUIT WITH FUSE/ANTI-FUSE TRANSISTOR WITH SELECTIVELY DAMAGED GATE INSULATING LAYER

CIRCUIT WITH FUSE/ANTI-FUSE TRANSISTOR WITH SELECTIVELY DAMAGED GATE INSULATING LAYER

机译:带有保险丝/反保险丝晶体管的电路,带有选择性损坏的门绝缘层

摘要

A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication.
机译:公开了一种半导体集成电路,其包括主晶体管和熔丝晶体管或反熔丝晶体管(“熔丝/反熔丝晶体管”)中的至少一个。每种晶体管类型包括:形成在半导体衬底中的有源区;栅堆叠,其包括依次形成在有源区上的栅绝缘层和栅电极;以及横跨栅堆叠而分开的源/漏区,但是栅绝缘层的栅绝缘层在制造期间,保险丝/反熔丝晶体管被选择性地损坏。

著录项

  • 公开/公告号US2008197911A1

    专利类型

  • 公开/公告日2008-08-21

    原文格式PDF

  • 申请/专利权人 JUN-HEE LIM;CHOONG-SUN SHIN;

    申请/专利号US20080029618

  • 发明设计人 CHOONG-SUN SHIN;JUN-HEE LIM;

    申请日2008-02-12

  • 分类号H01H37/76;

  • 国家 US

  • 入库时间 2022-08-21 20:16:30

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