TRANSISTOR HAVING SOURCE/DRAIN REGION ONLY UNDER SIDEWALL SPACER EXCEPT FOR CONTACTS AND METHOD

摘要

A transistor and related method are disclosed. The transistor may include a gate, a sidewall spacer formed along the gate, and a source/drain region positioned only under the sidewall spacer except for a portion at which a contact is positioned. The transistor may be ultra-low power and sub-threshold voltage or near sub-threshold voltage. The transistor may exhibit at least two times reduction in outer fringe capacitance (C_of).