Arithmetic processor for accomodating different field sizes

摘要

An arithmetic processor is provided, which comprises an arithmetic logic unit (ALU) containing arithmetic circuitry configured to perform field operations in an underlying field. The circuitry comprises a first controller for sequencing the ALU through steps in the field operations. The processor also comprises a register file comprising one or more general purpose registers to contain representations of one or more operands, and a second controller to provide instructions to the ALU for controlling computational operations of the ALU on the one or more operands. The second controller co-operates with the first controller to control operations of the ALU to accommodate different operand vector sizes in response to variations in size of the underlying field indicated by a field size control signal received by the second controller. The first controller monitors control bits and implements a counter in its own control registers for determining the size of a field being used.