A Flexible Operand Size Architecture for GF(2m) Arithmetic Processors.

摘要

Elliptic Curve Cryptographic (ECC) systems have gained a lot of attention due to their excellent security strength for relatively small key sizes. The most common and computationally intensive task in an ECC system is scalar point multiplications. Arithmetic operations such as, modular multiplication, inversion, and addition in Galois Fields (GF) operands are needed to perform this task. This dissertation proposes an architecture for these operations on GF(2m) operands, which could be used for various operands sizes without modifying or reconfiguring the underlying hardware. The architecture also uses power and/or clock gating techniques in order to save power in case a smaller key size is used. Four alternative designs of 512-bit architecture were implemented with Synopsys Design Compiler and Cadence SOC Encounter Place & Route tools using 45inn technology. Alternative designs could be used with a wide variety of applications, such as servers, workstations, personal computers, sensors, etc. The proposed architecture in this dissertation consumes much less power than conventional architectures and offers a high degree of flexibility at a high speed and small area.