A process for the preparation of an etch stop layer for a metallization layer having improved etching selectivity and better the inclusion of behavior

摘要

A semiconductor structure comprises a metal region (202,203) on which is a dielectric layer of low dielectric constant (204) with a barrier layer stack (250) comprising two dielectric layers (251,252) of different thickness in contact with the metal and dielectric layers respectively. An independent claim is also included for production processes for a dielectric layer barrier as above.