semiconductor memory with reduced fluctuation of writing speed

摘要

A non-volatile semiconductor memory is comprised of: a memory cell array (11) including a plurality of memory cells which is disposed at intersections of a plurality of bit lines and word lines and are connected to said bit lines; and a writing circuit (15) which receives an address signal (A m , A m-1 , ...) and supplies a bit line voltage (V bit ) to the bit line connected to the memory cell selected with the address signal (A m , A m-1 , ...) during writing operation. The writing circuit (15) changes, based on the address signal (A m , A m-1 , ...) , a level of the bit line voltage (V bit ) depending on a position of the selected memory cell in the memory cell array (11). The writing circuit (15) operates, based on the inputted writing address, to further increase a level of the bit line voltage (V bit ) supplied to the memory cell as the wiring distance via the bit line from the output end of the bit line voltage of the writing circuit (15) thereto is longer, fluctuation of writing speed in each memory cell of a memory cell array is reduced.