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CMOS IMAGE SENSOR CHIP SCALE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND METHOD OF THE PACKAGE

机译:带有通孔的芯片的CMOS图像传感器芯片大规模封装及其封装方法

摘要

PPROBLEM TO BE SOLVED: To provide a fan-out wafer level package structure that has no problem of mismatching caused by a coefficient of thermal expansion (CTE). PSOLUTION: The package structure comprises a substrate 2 with a die receiving through hole 4, a connecting through hole structure 22 and a first contact pad 3; a die 6 having a micro lens area 60 disposed in the die receiving through hole 4; a transparent cover 68 to cover the micro lens area 60; a surrounding material 24 formed under the die 6 and filled in the gap between the die 6 and sidewall of the die 6 receiving though hole 4; a dielectric layer 12 formed on the die 6 and the substrate 2; a re-distribution layer (RDL) 14 formed on the dielectric layer 12 and coupled to the first contact pad 3; a protection layer 26 formed over the RDL 14; a second contact pad 18 formed at the lower surface of the substrate 2 and under the connecting through hole structure 22; and a transparent base 68 formed on the protection layer 26. PCOPYRIGHT: (C)2009,JPO&INPIT
机译:

要解决的问题:提供一种扇出晶片级封装结构,该结构不存在因热膨胀系数(CTE)引起的不匹配问题。解决方案:封装结构包括衬底2,衬底2具有管芯容纳通孔4,连接通孔结构22和第一接触垫3;模具6具有微透镜区域60,该微透镜区域60布置在模具接收通孔4中;透明盖68覆盖微透镜区域60;围绕材料24形成在模具6的下方,并填充在模具6和模具6的容纳通孔4的侧壁之间的间隙中;形成在管芯6和基板2上的电介质层12;再分布层(RDL)14形成在介电层12上并耦合到第一接触垫3;在RDL 14上方形成的保护层26;第二接触垫18形成在基板2的下表面并且在连接通孔结构22下方;透明基底68形成在保护层26上。

COPYRIGHT:(C)2009,JPO&INPIT

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