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Manufacturing method of a semiconductor device including a nonvolatile memory having a plurality of memory cells including a selection transistor and a memory transistor

机译:包括具有非易失性存储器的半导体器件的制造方法,该非易失性存储器具有包括选择晶体管和存储晶体管的多个存储单元

摘要

Selection gate 1 is provided with selection transistors t1 and a floating gate , ( 2 ) and a control gate ( 3 ) memory transistor having a ( t2 ) including a plurality of memory cells ( mij ) is provided non-volatile memory and manufacturing method of a semiconductor device with . Semiconductor substrate 10 ) in a plurality of active semiconductor region a field oxide layer 12 ) in be separated from each other so as to form a . Then , surface 11 on the gate oxide film 14 and a conductive material of the first layer is formed by etching , selection gate 1 is formed a . Succeedlngly , surface so as to cross with the extending in a selection gate on the wall of the insulating material is provided with a . Selection gate and a gate oxide is adjacent to each other tunnel oxide film ( 18 ) with . The conductive material and the second layer 21 and the middle dielectric layer ( 25 ) and a conductive material the third layer 26 and depositing a . The third layer in the control gate ( 3 ) is selected on the gate extended and adjacent to each other so as to form a . Succeedlngly a control gate is used as a mask of the conductive material in second layer 2 is a floating gate etching a . By this method a selection gate thicker than the second conductive material depositing a layer of . , the intermediate dielectric layer and a conductive material of a third layer is deposited and before depositing the second layer for flattening . The memory cell is small and can be manufactured .
机译:选择栅1具有选择晶体管t1和浮置栅,(2)和具有(t2)包括多个存储单元(mij)的控制栅(3)存储晶体管被提供非易失性存储器及其制造方法。具有的半导体器件。在多个有源半导体区域中的半导体衬底10)中,将场氧化层12)彼此分开,以形成半导体衬底10)。然后,通过蚀刻形成栅氧化膜14上的表面11和第一层的导电材料,形成选择栅1。随后,在绝缘材料的壁上的选择栅中与延伸的表面交叉的表面设置有。选择栅和栅氧化层彼此相邻,隧道氧化膜(18)与栅氧化层相邻。导电材料和第二层21以及中间介电层(25)和导电材料第三层26并沉积α。在控制栅(3)中的第三层是在彼此延伸并彼此相邻的栅上选择的,以形成栅。随后,在第二层中使用控制栅极作为导电材料的掩模。通过这种方法,选择栅极的厚度比第二导电材料的沉积厚度大。在沉积第二层之前,沉积中间介电层和第三层的导电材料。存储单元很小,可以制造。

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