Support Structures for On-Wafer Testing of Wafer-Level Packages and Multiple Wafer Stacked Structures

摘要

A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.