Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same

摘要

A phase-locked loop (PLL) circuit includes a phase/frequency detector (PFD), a charge pump, a loop filter, a control circuit, a VCO, and a feedback circuit. The control circuit generates a digital control signal in response to the up signal, the down signal, and the oscillation-control voltage. The VCO generates an output signal of which a frequency is changed in response to the oscillation-control voltage and the digital control signal. Accordingly, the PLL circuit can automatically tune the frequency of the output signal of a VCO using a digital circuit having a simple structure.