首页> 外国专利> PHASE-LOCKED-LOOP CIRCUIT CAPABLE OF TUNING OSCILLATION FREQUENCY OF A VOLTAGE CONTROLLED OSCILLATOR AUTOMATICALLY AND DELAY-LOCKED LOOP CIRCUIT CAPABLE OF TUNING DELAY TIME OF A DELAY LINE AUTOMATICALLY

PHASE-LOCKED-LOOP CIRCUIT CAPABLE OF TUNING OSCILLATION FREQUENCY OF A VOLTAGE CONTROLLED OSCILLATOR AUTOMATICALLY AND DELAY-LOCKED LOOP CIRCUIT CAPABLE OF TUNING DELAY TIME OF A DELAY LINE AUTOMATICALLY

机译:能够自动调节电压控制振荡器的振荡频率的锁相环电路,并且能够自动调节延迟线的延迟时间的延迟锁定环电路

摘要

A phase-locked loop (PLL) circuit includes a phase/frequency detector (PFD), a charge pump, a loop filter, a control circuit, a VCO, and a feedback circuit. The control circuit generates a digital control signal in response to the up signal, the down signal, and the oscillation-control voltage. The VCO generates an output signal of which a frequency is changed in response to the oscillation-control voltage and the digital control signal. Accordingly, the PLL circuit can automatically tune the frequency of the output signal of a VCO using a digital circuit having a simple structure.
机译:锁相环(PLL)电路包括相位/频率检测器(PFD),电荷泵,环路滤波器,控制电路,VCO和反馈电路。控制电路响应于上升信号,下降信号和振荡控制电压而产生数字控制信号。 VCO产生输出信号,该输出信号的频率响应于振荡控制电压和数字控制信号而改变。因此,PLL电路可以使用具有简单结构的数字电路来自动调谐VCO的输出信号的频率。

著录项

  • 公开/公告号KR100717103B1

    专利类型

  • 公开/公告日2007-05-04

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20060020691

  • 发明设计人 KIM WOO SEOK;

    申请日2006-03-04

  • 分类号H03L7/08;

  • 国家 KR

  • 入库时间 2022-08-21 20:32:13

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