Electrostatic discharge testing method and semiconductor device fabrication method
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机译:静电放电测试方法和半导体器件制造方法
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摘要
A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, includes extracting an electrostatic discharge protection network including pads, nets and protective elements; setting start pads and end pads in the electrostatic discharge protection network; finding inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths from the start pads to the end pads; grouping together the electrostatic discharge current paths in the same order; calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads and groups to which the start pads and the end pads belong using a negative correlation between the inter-pad voltages and corresponding electrostatic withstand voltages; and determining whether the layout passes testing regarding electrostatic discharge.
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