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Method for manufacturing a floating-gate memory with high- and low-voltage transistors

机译:用高低压晶体管制造浮栅存储器的方法

摘要

The invention comprises an integrated circuit (100) including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer (24) outwardly from a semiconductor substrate (116), forming a floating gate layer (26) disposed outwardly from the tunnel oxide layer (24) and forming an insulator layer (28) disposed outwardly from the floating gate layer (26) to create a first intermediate structure. The method further includes the steps of masking a first region (114) and a second region (110) of the first intermediate structure leaving a third region (112) unmasked, removing at least a portion of the insulator layer (28), the floating gate layer (26) and the tunnel oxide layer (24) from the third region (112) and forming a first dielectric layer (42) disposed outwardly from the substrate (116) in a region approximately coextensive with the third region (112). The second region (110) and the third region (112) are masked, leaving the first region (114) unmasked. Then, at least a portion of the insulator layer (28), the floating gate layer (26) and the tunnel oxide layer (24) is removed from the first region (114) . A second dielectric layer (44) is formed outwardly from the substrate (116) and the first dielectric layer (42) in a region approximately coextensive with the first region (114) and the third regions (112), respectively.
机译:本发明包括集成电路(100),其包括集成的高压和低压外围晶体管以及制造该集成电路的方法。在本发明的一个方面,一种将高低压晶体管集成到浮栅存储器阵列中的方法包括以下步骤:从半导体衬底(116)向外形成隧道氧化层(24),形成浮栅层(26)。绝缘层(28)从隧道氧化物层(24)向外布置,并形成从浮栅层(26)向外布置的绝缘体层(28),以形成第一中间结构。该方法还包括以下步骤:掩蔽第一中间结构的第一区域(114)和第二区域(110),而使第三区域(112)未被掩蔽,去除绝缘体层(28)的至少一部分,浮置。栅层(26)和隧道氧化物层(24)从第三区域(112)开始,并形成第一介电层(42),该第一介电层(42)从衬底(116)向外布置在与第三区域(112)大致相同的区域内。第二区域(110)和第三区域(112)被掩蔽,而第一区域(114)未被掩蔽。然后,从第一区域(114)去除绝缘体层(28),浮栅层(26)和隧道氧化物层(24)的至少一部分。从衬底(116)和第一介电层(42)分别在与第一区域(114)和第三区域(112)大致共同延伸的区域中向外形成第二介电层(44)。

著录项

  • 公开/公告号EP0913862B1

    专利类型

  • 公开/公告日2009-08-19

    原文格式PDF

  • 申请/专利权人 TEXAS INSTRUMENTS INC;

    申请/专利号EP19980308797

  • 发明设计人 ASHBURN STATON P.;KAYA CETIN;

    申请日1998-10-27

  • 分类号H01L21/8239;H01L21/8247;

  • 国家 EP

  • 入库时间 2022-08-21 19:19:23

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