Single-Crystal C_(60) Needle/CuPc Nanoparticle Double Floating-Gate for Low-Voltage Organic Transistors Based Non-Volatile Memory Devices

摘要

Field-effect transistor (FET)-type memory devices have been widely investigated recently because of their non-destructive read-out property, single transistor realization, and excellent compatibility with complementary metal oxide semiconductor (CMOS) devices. Among them, floating-gate memory based on a FET structure has an electrically isolated conducting gate, which can be used as charge storage sites for charging or discharging during the programming and erasing processes. Precise control of the amount of charge stored in the specific floating-gate to set the bits of a memory cell could solve the fundamental scaling-down problem and meet the requirement for high-density memory devices. Therefore, a discrete floating-gate utilizing nanostructured materials rather than a conventional planar floating-gate can determine the size and density of charge-trapping elements in a uniform distribution for future superior high-density memory. The following possibilities have already been employed to fashion nanostructured floating-gate devices: ⅰ) thermal evaporation of thin metal layers or metal islands (nanoparticles (NPs)); ⅱ) chem-isorbed or electrostatic self-assembled metal monolayers; ⅲ) block polymer/NP composites; ⅳ) carbon-based charge trapping materials, such as C_(60) or graphene. However, the above floating-gate-based memory devices generally utilize a single floating-gate that stores only one kind of charge (hole or electron) to signify a "1" or "0" digital state as one bit of information. To meet the future demand for product miniaturization and high density, memory properties such as memory window, retention, endurance, and integration still need to be enhanced. If two floating-gates were assembled in one device, the memory device could potentially store data at higher density in the same physical space during the non-volatile mode and also suppress leakage of the stored charge as a result of the band offset or Coulomb repulsion between the upper and lower floating-gates. On the other hand, memories that allow the coexistence of trapping charges in both polarities (ambi-polar trapping) result in a large bi-directional threshold voltage shift and correspondingly large memory window for designing multi-level flash memory. However, optimizing the memory materials and structures to enable continuous scaling has remained a significant challenge until now. In particular, the detailed mechanism and design principles for organic nonvolatile memory with a double floating-gate are not clear.