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SEMICONDUCTOR FABRICATION PROCESS USING ETCH STOP LAYER TO OPTIMIZE FORMATION OF SOURCE/DRAIN STRESSOR

机译:利用蚀刻停止层优化源/漏应力管形成的半导体制造过程

摘要

A semiconductor fabrication process includes forming an etch stop layer (ESL) (109) overlying a buried oxide (BOX) layer (102) and an active semiconductor layer (105) overlying the ESL. A gate electrode (112) is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors (130) are formed on the ESL where the source/drain stressors strain the transistor channel (115). Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75‹ C may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors. ® KIPO & WIPO 2009
机译:半导体制造工艺包括形成覆盖在掩埋氧化物(BOX)层(102)上的蚀刻停止层(ESL)(109)和覆盖ESL的有源半导体层(105)。在有源半导体层上形成栅电极(112)。蚀刻有源半导体层的源/漏区以暴露ESL。源极/漏极应力源(130)形成在ESL上,其中源极/漏极应力源使晶体管沟道(115)应变。形成ESL可以包括外延生长具有大约30nm或更小的厚度的硅锗ESL。优选地,有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。使用加热到大约75°C的NH4OH:H2O溶液进行的湿法刻蚀可用于刻蚀源/漏区。 ESL可以是具有第一百分比的锗的硅锗。对于P型晶体管,源极/漏极应力源可以是锗具有第二百分比的硅锗,对于N型晶体管,源极/漏极应力源可以是硅碳。 ®KIPO和WIPO 2009

著录项

  • 公开/公告号KR20080108498A

    专利类型

  • 公开/公告日2008-12-15

    原文格式PDF

  • 申请/专利权人 FREESCALE SEMICONDUCTOR INC.;

    申请/专利号KR20087023819

  • 发明设计人 ZHANG DA;NGUYEN BICH YEN;WHITE TED;

    申请日2008-09-29

  • 分类号H01L29/78;H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 19:14:29

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