Clock monitoring circuit for e.g. application-specific integrated circuit, has testing circuit for testing whether next level change of detailed clock signal takes place, before and after testing clock signal

摘要

The monitoring unit (100) has a testing circuit (106) connected with a delay circuit (104) and a clock input (102). The testing circuit tests whether a next level change of a detailed clock signal waiting for a half of a nominal elementary period duration takes place after a level change of the detailed clock signal, both after a testing clock signal and before another testing clock signal. The testing circuit outputs an appropriate clock warning signal when the level change of the detailed clock signal does not take place.