Built-in test for logic circuits with multiple clocks

摘要

This paper presents an at-speed built-in test method to test for logic circuits with multiple clocks. The proposed method makes use of the LFSR reseeding technique, and specified a release and a capture clocks for each seed. At-speed testing for all pairs of clocks reduces difficulties on timing design. We also describe a test generation and seed generation methods that take multiple clocks into consideration in order to achieve complete coverage for stuck-at and transition faults with Small test length and small data volume. Experimental results for ISCAS benchmark circuits with multiple clocks demonstrate that effectiveness of our approach.