Test circuit has decoder clocked by high frequency clock signal that generates internal control signals for test circuit depending on control signals applied to control signal input bus

摘要

The test circuit (1) has a frequency multiplier circuit (8), a control signal input bus (14), a parallel-serial converter (17) and a decoder circuit (19) clocked by the high frequency clock signal that generates internal control signals for the test circuit depending on control signals applied to the control signal input bus.