Strange programmable non-volatile storage with NOR architecture

摘要

A nonvolatile memory (1) having a NOR architecture has a memory array (2) including a plurality of memory cells (3) arranged in rows and columns in NOR configuration, the memory cells (3) arranged on a same column being connected to one of a plurality of bit lines (11); and a column decoder (6). The column decoder comprises a plurality of selection stages (17), each of which is connected to respective bit lines (11) and receives first bit line addressing signals (YM0, ..., YM7). The selection stages (17) comprise word programming selectors (28) controlled by the first bit line addressing signals (YM0, ..., YM7) and supplying a programming voltage (70) to only one of the bit lines (11) of each selection stage (17). Each selection stage (17) moreover comprises a string programming selection circuit (29, 30) controlled by second bit line addressing signals (S0, ..., S7) thereby simultaneously supplying the programming voltage (70) to a plurality of the bit lines (11) of each selection stage (17). IMAGE IMAGE