Frequency locked loop with fractional division function in forward path

摘要

The present invention provides a circuit for receiving an input signal having a first frequency and generating an output signal having a second frequency. The circuit comprises a forward branch for receiving the input signal and generating the output signal and a return branch for generating a feedback signal from the output signal. The forward branch comprises a frequency ratio detector 52 (fig.5) for receiving the input signal and the feedback signal and outputting a value based on a ratio of a frequency of the feedback signal to the first frequency; a word length reduction block 54, such as a sigma delta modulator, for receiving a fractional component k of a first division factor and generating a modulated output; an adder 56 for forming a sum of an integer component M of the first division factor and the modulated output of the word length reduction block; a subtracting element 58 for subtracting the output value of the frequency detector from the sum; and an oscillator 62 controlled by an output from the subtracting element. The advantage of the invention is that the 'resolution' of the system is not thrown away until after the frequency detecting stage.