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Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division

机译:频分引起的电荷泵锁相环中相位噪声频谱的折叠

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In charge-pump phase-locked loops (CP-PLLs), the reference signal samples the phase delay between reference and feedback signals. When a frequency divider is present in the loop, the spectrum folding of the voltage-controlled oscillator phase noise caused by the inherent subsampling operation adds a relevant contribution to the in-band output noise. This brief elaborates the discrete-time linear model of PLLs to take into account spectrum folding and provides a simple equation for the estimation of the output noise. The closed-form expressions are validated on the basis of behavioral simulations of a third-order CP-PLL.
机译:在电荷泵锁相环(CP-PLL)中,参考信号对参考信号和反馈信号之间的相位延迟进行采样。当环路中存在分频器时,由固有的二次采样操作引起的压控振荡器相位噪声的频谱折叠会增加带内输出噪声。本文简要阐述了PLL的离散时间线性模型,以考虑频谱折叠,并为估算输出噪声提供了一个简单方程式。基于三阶CP-PLL的行为仿真对闭合形式的表达式进行了验证。

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