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Pixel cache for 3D graphics circuit

机译:3D图形电路的像素缓存

摘要

Apparatus including a memory device, and hardware entities, and the sub-image cell value cache, and a cache write operator is provided. At least some of the hardware entity and performs the operations, including the use of device memory and access to the device memory. Hardware entity, including 3D graphics processing circuit for displaying 3D images from the primitive object. It is separated from the device memory, cache, is provided to hold data including a sub-image cell values ​​are buffered. The cache, instead of accessing directly to the sub-image cell values ​​in the device memory, and access the sub-image cell values ​​buffered in the cache, pixel processing portion of the 3D graphics circuit is connected to the 3D graphic circuit. Under the direction of the priority scheme, write operator writes to the memory device, the sub-image cell values ​​are buffered. Priority scheme, save in the cache boundary cell values ​​bounding the primitive one or more objects.
机译:提供了一种设备,该设备包括存储设备,硬件实体,子图像单元值高速缓存以及高速缓存写操作器。至少一些硬件实体执行操作,包括使用设备内存和访问设备内存。硬件实体,包括3D图形处理电路,用于显示来自原始对象的3D图像。它与设备内存分开,提供缓存,以保存包含子图像单元值被缓存的数据。 3D图形电路的像素处理部分连接到3D图形,而不是直接访问设备存储器中的子图像单元值并访问缓存中缓冲的子图像单元值电路。在优先级方案的指导下,写操作符写入存储设备,子图像单元值被缓冲。优先级方案,在缓存的边界中保存与原始对象绑定的一个或多个对象的值。

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