首页> 外国专利> Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions

Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions

机译:半导体器件部分具有亚波长尺寸的栅电极导电结构,该结构由沿至少四个栅电极轨道定义的矩形形状的栅电极布局特征形成,并具有相应的非对称扩散区域

摘要

A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The conductive features within the gate electrode level region are defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features.
机译:半导体器件的衬底部分形成为包括多个扩散区域,该扩散区域相对于为将衬底部分一分为二的虚拟线以非对称方式定义。栅电极水平区域形成在衬底部分上方,以包括限定为仅在第一平行方向上延伸的多个导电特征。栅电极级区域内的多个导电特征中的每一个均由相应的起始矩形布局特征制成。沿着第一平行方向上的至少四个不同的虚拟延伸范围线定义栅电极级区域内的导电特征。垂直于第一平行方向测量栅电极级区域内的导电特征的宽度尺寸,并且小于在光刻工艺中用于制造导电特征的光的波长。

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