INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL

摘要

A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.