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Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof

机译:装有多个存储宏的半导体器件及其测试方法

摘要

According to the present invention, an intra-macro match determining circuit 111 internally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus, the determination result for a match is combined with the test outputs instead of a particular value. Consequently, the same expected value can also be used for individual macro testing, and output bits are assigned to each of the macros. Therefore, in internally performing a comparison with the expected value, the tester can easily detect defective macros.
机译:根据本发明,宏内匹配确定电路 111 在内部确定每个宏的n个测试输出是否都具有相同的电平。确定的结果与一些测试输出组合,然后将结果信号输出到测试仪。因此,用于匹配的确定结果与测试输出而不是特定值组合。因此,相同的期望值也可以用于单独的宏测试,并且将输出位分配给每个宏。因此,在内部与期望值进行比较时,测试仪可以容易地检测出有缺陷的宏。

著录项

  • 公开/公告号US7688658B2

    专利类型

  • 公开/公告日2010-03-30

    原文格式PDF

  • 申请/专利权人 NAOKI YAMADA;

    申请/专利号US20080102561

  • 发明设计人 NAOKI YAMADA;

    申请日2008-04-14

  • 分类号G11C7/00;

  • 国家 US

  • 入库时间 2022-08-21 18:48:58

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