首页> 外国专利> Pattern data verification method for semiconductor device, computer-readable recording medium having pattern data verification program for semiconductor device recorded, and semiconductor device manufacturing method

Pattern data verification method for semiconductor device, computer-readable recording medium having pattern data verification program for semiconductor device recorded, and semiconductor device manufacturing method

机译:用于半导体装置的图案数据验证方法,具有记录了用于半导体装置的图案数据验证程序的计算机可读记录介质以及半导体装置制造方法

摘要

A pattern data verification method for a semiconductor device, including extracting, from design data, design data corresponding to an edge portion of a mask pattern to obtain an edge portion of a pattern on a substrate to be processed, when the pattern is obtained on the substrate to be processed by using at least two masks each having the mask pattern corresponding to the design data, setting allowable errors with respect to the extracted design data and the design data which is not extracted, respectively, calculating a pattern formed on the substrate to be processed by using at least one mask by process simulation, and comparing an error between the pattern calculated by the simulation and the design data with the allowable error set for the design data.
机译:一种用于半导体器件的图案数据验证方法,包括从设计数据中提取与掩模图案的边缘部分相对应的设计数据,以在待处理基板上获得图案时获得图案的边缘部分。通过使用至少两个分别具有与设计数据相对应的掩模图案的掩模进行处理的基板,分别对所提取的设计数据和未被提取的设计数据设置容许误差,从而计算在基板上形成的图案以通过使用至少一个掩模通过工艺仿真来进行加工,并将由仿真计算出的图案与设计数据之间的误差与为设计数据设置的容许误差进行比较。

著录项

  • 公开/公告号US7730445B2

    专利类型

  • 公开/公告日2010-06-01

    原文格式PDF

  • 申请/专利权人 SHIGEKI NOJIMA;

    申请/专利号US20070798725

  • 发明设计人 SHIGEKI NOJIMA;

    申请日2007-05-16

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 18:48:49

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