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Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions
Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions
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机译:半导体器件在不同器件区域中具有不同固有应力的应力蚀刻停止层,并具有不同设计的PN结
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摘要
By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.
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