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Integral patterning of large features along with array using spacer mask patterning process flow
Integral patterning of large features along with array using spacer mask patterning process flow
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机译:使用间隔物掩模图案化工艺流程对大型特征和阵列进行整体图案化
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摘要
Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.
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