The present invention is related to a method for determining time to failure characteristics of a microelectronics device, comprising the steps of: providing a test structure, being a parallel connection of a plurality of such on-chip interconnects; performing measurements on the test structure under test conditions for current density and temperature, said test structure being such that failure of one of the on-chip interconnects within the parallel connection changes the test conditions for at least one of the other individual on-chip interconnects of the parallel connection; determining from the measurements time to failure characteristics, whereby the change in the test conditions is compensated for.
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