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WAFER LEVEL CHIP SIZE PACKAGE HAVING A PATTERNED RESIN SEALING PART WHICH IS FORMED IN ONLY A PARTIAL PORTION OF A WAFER AND A MANUFACTURING METHOD THEREOF
WAFER LEVEL CHIP SIZE PACKAGE HAVING A PATTERNED RESIN SEALING PART WHICH IS FORMED IN ONLY A PARTIAL PORTION OF A WAFER AND A MANUFACTURING METHOD THEREOF
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机译:具有仅部分硅片组成的树脂密封部件的硅片级芯片尺寸包装及其制造方法
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摘要
PURPOSE: A wafer level chip size package having a patterned resin sealing part and a manufacturing method thereof are provided to relieve the bent degree of a wafer by forming the resin sealing part on only a portion of the wafer.;CONSTITUTION: A wafer level chip size package(200) having a patterned resin sealing part includes a semiconductor substrate, the first insulation layer, a re-wiring layer, the second insulation layer, a solder ball, and a resin sealing part. A bonding pad is formed on the semiconductor substrate. The first insulation layer is formed in an upper side of the semiconductor substrate. The first insulation layer includes the first opening through which the bonding pad can be exposed. The re-wiring layer is extended and formed from the bonding pad to an upper part of the first insulation layer and has a connection pad. The second insulation layer is formed in an upper part the re-wiring layer and the first insulation layer. The second insulation layer includes the second opening for exposing the connection pad. A solder ball(270) is formed in the connection pad. The resin sealing part(290) covers the solder ball and the second insulation layer(260) and is patterned so that the solder ball and the second insulation layer can have an exposed area.;COPYRIGHT KIPO 2010
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