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Development of Resin Strress Buffer Layer Type Wafer Level Chip Size Package with High Reliability for Board Level Test

机译：开发树脂应力缓冲层型晶片型芯片尺寸封装，具有高可靠性的板级测试

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Nobuaki HASHIMOTO; Shuichi TANAKA; Shunpei OGAYA; Haruki ITO;
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年度 2008
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1. Structural design optimization for board-level drop reliability of wafer-level chip-scale packages [J] . Tsung-Yueh Tsai, Yi-Shao Lai, Chang-Lin Yeh, Microelectronics reliability . 2008,第5期

机译：晶圆级芯片级封装的板级跌落可靠性的结构设计优化
2. Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages [J] . Yi-Shao Lai, Chang-Lin Yeh, Ching-Chun Wang Journal of Electronic Packaging . 2007,第1期

机译：晶圆级芯片级封装的板级跌落可靠性研究
3. Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages [J] . Yi-Shao Lai, Chang-Lin Yeh, Ching-Chun Wang Journal of Electronic Packaging . 2007,第1期

机译：晶圆级芯片级封装的板级跌落可靠性研究
4. Reliability Improvement of Resin Stress Buffer Layer Type Wafer Level Chip Size Package for Automotive Applications [C] . Shunpei OGAYA, Shuichi TANAKA, Haruki ITO, IMAPS 2008 - 41st international symposium on microelectronics: bringing together the entire microelectronics supply chain . 2008

机译：汽车应用树脂应力缓冲层型晶圆级芯片尺寸封装的可靠性改进
5. Fabrication of CZTS solar cells by sputtering method An experimental technique to measure the resistance change of ITO thin film during cyclic bending Reliability study of wafer level chip scale package using board level drop test. [D] . Ramesh, Dasharathy N. 2013

机译：溅射法制备CZTS太阳能电池循环弯曲过程中测量ITO薄膜电阻变化的实验技术使用板级跌落试验研究晶圆级芯片规模封装的可靠性。
6. Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests [O] . Chang-Chun Lee 2017

机译：晶圆级底部填充对热循环测试过程中超薄芯片堆叠式3D-IC组件微凸点可靠性的影响
7. Drop Test Reliability of Wafer Level Chip Scale Packages [O] . 2012

机译：晶圆级芯片级封装的跌落测试可靠性

Development of Resin Strress Buffer Layer Type Wafer Level Chip Size Package with High Reliability for Board Level Test

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