首页>
外国专利>
WAFER LEVEL PACKAGE, CHIP SIZE PACKAGE DEVICE AND METHOD OF MANUFACTURING WAFER LEVEL PACKAGE
WAFER LEVEL PACKAGE, CHIP SIZE PACKAGE DEVICE AND METHOD OF MANUFACTURING WAFER LEVEL PACKAGE
展开▼
机译:晶片水平包装,芯片尺寸包装装置和制造晶片水平包装的方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
A wafer level package (20A) according to the present invention is provided with a base wafer (22) having a plurality of semiconductor chips (1) mounted or formed on its surface and a cover wafer (23) opposite the base wafer (22). The base wafer (22) and the cover wafer (23) are joined so as to sandwich therebetween a frame-shaped seal frame (4) which seals the periphery of each semiconductor chip. A gap (24) is formed between respective seal frames (4) of mutually adjoining semiconductor chips (1). In the gap (24) between the respective seal frames (4) of the mutually adjoining semiconductor chips (1), a partial connect part (26) is provided, which mutually and partially connects both seal frames (4). Hereby, the occurrence of a crack in a seal frame can be avoided when dicing, while providing a wafer level package, a chip size package device and a method of manufacturing a wafer level package, which can suppress the occurrence of peel-off from a wafer even when a high-temperature process is applied after a wet process or after liquid cleaning.
展开▼