OUTPUT CONTROL SCAN FLIP-FLOP, SCAN TEST CIRCUIT WITH THE USE OF THE SAME, AND TEST DESIGNING METHOD

摘要

PROBLEM TO BE SOLVED: To obviate the need of a delay test controller or a plurality of DELAY TEST MODE signal lines to reduce a size of a circuit.;SOLUTION: An output control scan flip-flop 1 can control holding and inverting of an output value irrespective of an input value. The output control scan flip-flop 1 includes a scan flip-flop 3, a memory device 2 that operates in synchronization with a clock signal and stores first input data input from an external device, a non-exclusive logical sum circuit 4 for inputting an output signal of the memory device 2 and an output signal of the scan flip-flop 3, and a selector 5 that inputs a second input data input from an external device, an output signal of the non-exclusive logical sum circuit 4 and a select signal from an external device, and outputs an output signal to be input to the scan flip-flop 3.;COPYRIGHT: (C)2011,JPO&INPIT