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High voltage ESD LDMOS-SCR with gate reference voltage
High voltage ESD LDMOS-SCR with gate reference voltage
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机译:具有栅极参考电压的高压ESD LDMOS-SCR
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摘要
In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.
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