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Processing apparatus for storing branch history information in predecode instruction cache

机译:用于将分支历史信息存储在预解码指令高速缓存中的处理设备

摘要

The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information indicating that the input instruction is a conditional branch instruction and instruction type information indicating a type of the conditional branch instruction when the input instruction is a conditional branch instruction, and writing the input instruction, from which the operation code is deleted, the conditional branch instruction information and the instruction type information to the instruction cache memory, and a history information writing unit writing history information indicating whether or not the conditional branch instruction was branched, as a result of executing the conditional branch instruction stored in the instruction cache memory, to an area in the instruction cache memory, where the operation code of the conditional branch instruction is deleted.
机译:本发明提供一种信息处理设备,该信息处理设备具有预解码器,该预解码器对输入指令中的操作码进行解码,并在输入时生成指示该输入指令为条件分支指令的条件分支指令信息和指示该条件分支指令的类型的指令类型信息。指令是条件分支指令,将要从中删除了操作码的输入指令,条件分支指令信息和指令类型信息写入指令高速缓冲存储器,历史信息写入单元将表示是否由于执行了在指令高速缓冲存储器中存储的条件转移指令的结果,条件转移指令被转移到指令高速缓冲存储器中的区域,在该区域中删除了条件转移指令的操作代码。

著录项

  • 公开/公告号US7877578B2

    专利类型

  • 公开/公告日2011-01-25

    原文格式PDF

  • 申请/专利权人 YASUHIRO YAMAZAKI;

    申请/专利号US20080071586

  • 发明设计人 YASUHIRO YAMAZAKI;

    申请日2008-02-22

  • 分类号G06F9/30;G06F9/40;G06F15/00;

  • 国家 US

  • 入库时间 2022-08-21 18:08:29

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