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Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
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机译:用于每条指令高速缓存行选择存储在推测分支目标地址高速缓存中的多个目标地址之一的设备和方法
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摘要
An apparatus and method in a pipelined microprocessor for selecting one of a plurality of branch target addresses cached in a branch target address cache (BTAC) within a line selected by an instruction cache fetch address. The invention enables support for speculatively branching to one of a plurality of branch instructions potentially cached in an instruction cache line selected by the fetch address. Each target address has cached with it in the BTAC an associated offset within the instruction cache line of the previously executed associated branch instruction as well as a valid bit and a prediction of whether the branch instruction will be taken or not taken. Control logic selects the first, valid, taken, and seen target address. The target address is “seen” if the associated offset is greater than or equal to a corresponding portion of the least significant bits of the fetch address.
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