首页> 外国专利> System for reducing number of lookups in a branch target address cache by storing retrieved BTAC addresses into instruction cache

System for reducing number of lookups in a branch target address cache by storing retrieved BTAC addresses into instruction cache

机译:通过将检索到的BTAC地址存储到指令高速缓存中来减少分支目标地址高速缓存中查找次数的系统

摘要

A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch target address is associated with the instruction address. The branch target address retrieved from the BTAC is stored in the I-cache. With this disclosed technique, subsequent instruction addresses are looked up in the I-cache, nonparallel to the BTAC, thus saving power by reducing needless BTAC lookups.
机译:公开了一种用于减少对分支目标地址高速缓存(BTAC)的查找的技术。在该技术中,响应于在指令高速缓存(I-cache)中查找指令地址的未命中,从BTAC检索分支目标地址。分支目标地址与指令地址相关联。从BTAC检索到的分支目标地址存储在I缓存中。利用该公开的技术,在I高速缓存中查找与BTAC不平行的后续指令地址,从而通过减少不必要的BTAC查找来节省功率。

著录项

  • 公开/公告号US7640422B2

    专利类型

  • 公开/公告日2009-12-29

    原文格式PDF

  • 申请/专利权人 MICHAEL WILLIAM MORROW;

    申请/专利号US20060464996

  • 发明设计人 MICHAEL WILLIAM MORROW;

    申请日2006-08-16

  • 分类号G06F9/32;

  • 国家 US

  • 入库时间 2022-08-21 18:47:40

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