Apparatus for superscalar instruction predecoding using cached instruction lengths

摘要

A method and apparatus for eliminating the delay in a parallel processing pipeline. In a parallel processing pipeline system, a circuitry is provided to determine the length and align two instructions in parallel. Parallel decoding circuitry is provided for decoding and executing the two instructions. A branch prediction cache stores the target instruction and next sequential instruction, and is tagged by the address of the branch instruction, as in the prior art. In addition, however, the branch prediction cache also stores the length of the first and second instructions and the address of the second instruction. This additional data allows the target and next sequential instructions to be directly aligned and presented to the parallel decoding circuits without waiting for a calculation of their lengths and starting addresses.