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Predecoded Instruction Cache

机译:预解码指令缓存

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One thing I hadn't noted is that if the code is executed serially, it should probably still all be decoded at the time of fetching, and so pre-decoded instructions should be what is cached. That is what K9 did . . . Athlon used 3 bits per byte to aid decode conveying which bytes were the Opcode, which bytes were R/M and SIB, and the end of the instruction byte. Opteron got rid of 2 of those bits and just used the end marker but added a stage in the decode pipeline.
机译:我没有注意到的一件事是,如果代码是串行执行的,则在获取时可能仍应将其全部解码,因此预解码的指令应该是缓存的内容。那就是K9所做的。 。 。 Athlon每字节使用3位以帮助解码,以传达哪些字节是操作码,哪些字节是R / M和SIB,以及指令字节的末尾。 Opteron除去了其中的2位,只使用了结束标记,但在解码管线中添加了一个阶段。

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