DATA BUFFER CONTROLLING CIRCUIT, CAPABLE OF GENERATING AN INTERNAL COMMAND SIGNAL BY COMBINING LEVELS OF EXTERNAL COMMAND SIGNALS, AND A SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A data buffer controlling circuit and a semiconductor memory device are provided to secure sufficient margin between a data buffer enable timing and a data input timing by advancing the data buffer enable timing.;CONSTITUTION: An internal command signal generating part(11) generates an internal command signal. A first logical element obtains the inverting signal of delaying command signals(CSBD, RASBD) and implements a logical operation. A second logical element obtains another delaying command signals(CASBD, WEBD) and implements the logical operation. A logical part implements the logical operation by obtaining the output signal of the logical elements. A buffer enable signal generating part(12) is synchronized with the falling edge of an internal clock signal in order to generate the buffer enable signal.;COPYRIGHT KIPO 2011