Semiconductor memory device for processing internal command signals, addresses and data input/output uses an internal timing signal inverted by an external timing signal, logical combination circuits and clock pulse generators.

摘要

A clock pulse generator (22) has a logical combination circuit (24) to receive an external timing signal (XCLK) and a test mode signal (TM) and to deliver non-inverted and inverted signals (A11,A12) from the external timing signal. The logical combination circuit has a first path of first (INV1) and second (INV2) inverters interconnected in series to generate a non-inverted timing signal.