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CLOCK TREE DESIGN DEVICE AND CLOCK TREE DESIGN METHOD

机译:时钟树设计装置和时钟树设计方法

摘要

PROBLEM TO BE SOLVED: To make a clock skew and the number of buffers relatively small under a condition for minimization of clock latency.SOLUTION: A clock tree design device includes an equal-distance point set calculation part which finds a set of equal-distance points such that a Manhattan distance from a target sink and a Manhattan distance from a farthest sink are equal to each other; a path setting block setting part which sets a path setting block area for setting a path length of a clock path to a shortest Manhattan distance; a branch point setting part which sets a point at the farthest distance from a clock source in the path setting block area of the set of equal-distance points as a branch point; and a path setting part which sets a common path between the target sink and farthest sink in the path setting block area from the clock source to the branch point, and sets a clock path from the branch point to the target sink and a clock path from the branch point to the farthest sink to be at a shortest Manhattan distance.
机译:解决的问题:在最小化时钟等待时间的条件下使时钟偏斜和缓冲区数量相对较小。解决方案:时钟树设计设备包括一个等距点集计算部分,该部分可找到一组等距点使得目标水槽的曼哈顿距离与最远水槽的曼哈顿距离彼此相等的点;路径设置块设置部分,其设置用于将时钟路径的路径长度设置为最短曼哈顿距离的路径设置块区域;分支点设定部,在该等距离点的集合的路径设定块区域中,将距时钟源最远的点设定为分支点。路径设定部,设定从时钟源到分支点的路径设定块区域中的目标宿和最远的宿之间的公共路径,并设定从分支点到目标宿的时钟路径以及从分支点到目标宿的时钟路径。分支指向最远水槽的距离是曼哈顿最短的距离。

著录项

  • 公开/公告号JP2012194888A

    专利类型

  • 公开/公告日2012-10-11

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP20110059454

  • 发明设计人 SHIRAI TOSHIAKI;ISHIOKA TAKASHI;

    申请日2011-03-17

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-21 17:44:58

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