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Hierarchical clock line tree design method for application specific integrated circuit, involves connecting clock line trees of same structure with clock signal input terminals of hierarchical structures
Hierarchical clock line tree design method for application specific integrated circuit, involves connecting clock line trees of same structure with clock signal input terminals of hierarchical structures
An integrated circuit (1) has hierarchical structures (11-13) with clock signal input terminals (14-16,17-20,21). The clock line trees of same structure are connected with the input terminals.
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