首页>
外国专利>
AUTOMATIC LAYOUT WIRING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, LAYOUT DEVICE, AUTOMATIC LAYOUT WIRING PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT
AUTOMATIC LAYOUT WIRING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, LAYOUT DEVICE, AUTOMATIC LAYOUT WIRING PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT
展开▼
机译:半导体集成电路的自动布局布线方法,布局设备,自动布局布线程序和半导体集成电路
展开▼
页面导航
摘要
著录项
相似文献
摘要
PROBLEM TO BE SOLVED: To provide a clock tree scarcely affected by variation (OCV: on chip variation) in a chip and facilitating a timing closure.;SOLUTION: This automatic layout wiring method of a semiconductor integrated circuit using a layout device, determines the difficulty of a timing closure between respective logic paths based on a timing analysis result to a semiconductor integrated circuit generated by an automatic cell layout process; and generates a clock tree of a path whose timing closure difficulty exceeds a prescribed level in such a manner that branches among logic circuit elements constituting the path become less than the branches of a path whose timing closure difficulty is the prescribed level or less.;COPYRIGHT: (C)2012,JPO&INPIT
展开▼