LAYOUT VERIFICATION DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT VERIFICATION METHOD

摘要

PROBLEM TO BE SOLVED: To automatically check ion implantation in the design phase.SOLUTION: A layout verification device relating to an embodiment comprises: a first verification part 60 for verifying whether or not an element extracted from a layout of semiconductor integrated circuit is as described in a circuit diagram; and a second verification part 70 for verifying whether or not the layout of semiconductor integrated circuit complies with design rules extracted from specification information. A filter processing part included in one of the first and second verification parts 60 and 70 executes an AND logic among a verified element, mask data necessary to form the verified element and reverse data of mask data unnecessary to form the verified element, and determines whether or not ion implantation is executed appropriately to the verified element.