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In the semiconductor integrated circuit design support device which simulation is done the semiconductor integrated circuit design support device, semiconductor integrated circuit

机译:在完成模拟的半导体集成电路设计支持装置中,半导体集成电路设计支持装置,半导体集成电路

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit design support device, a semiconductor integrated circuit support method, and a semiconductor integrated circuit design support program for simulating a gate level netlist without rewriting a test bench even when a signal included in an RTL to be monitored in the simulation of the RTL is not included in the gate level netlist.;SOLUTION: A semiconductor integrated circuit design support device 200 is provided with an equivalent signal extraction part 290 for extracting a signal equivalent to a signal to be monitored in an RTL from a netlist. When any signal to be monitored in the RTL is not included in the gate level netlist, the signal extracted from the equivalent signal extraction part 190 is used as the signal to be monitored, and the gate level netlist is simulated.;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:提供一种半导体集成电路设计支持装置,一种半导体集成电路支持方法和一种半导体集成电路设计支持程序,即使在RTL中包含的信号被发送到该网络时,也无需重写测试台就可以模拟门级网表。解决方案:半导体集成电路设计支持设备200配备有等效信号提取部分290,用于提取与要在RTL仿真中监视的信号等效的信号。来自网表的RTL。当在RTL中要监视的任何信号未包括在门级网表中时,将从等效信号提取部分190中提取的信号用作要监视的信号,并且模拟门级网表。 )2009,日本特许厅

著录项

  • 公开/公告号JP4881769B2

    专利类型

  • 公开/公告日2012-02-22

    原文格式PDF

  • 申请/专利权人 株式会社リコー;

    申请/专利号JP20070069650

  • 发明设计人 塚本 泰隆;

    申请日2007-03-16

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 17:36:55

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