首页> 外国专利> DESIGN SUPPORT SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN SUPPORT PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

DESIGN SUPPORT SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN SUPPORT PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

机译:半导体集成电路的设计支持系统,半导体集成电路的设计方法,半导体集成电路的设计支持程序以及半导体集成电路的制造方法

摘要

PPROBLEM TO BE SOLVED: To provide a design support system for a semiconductor integrated circuit, a design method for the semiconductor integrated circuit, a design support program for the semiconductor integrated circuit, and a manufacturing method for the semiconductor integrated circuit, capable of raising a replacement rate from a single cut via to multi-cut bear and improving the reliability and manufacturing yield of the semiconductor integrated circuit. PSOLUTION: The design support system is provided with: a global routing means 13 for allotting a global routing path 22 to a routing area, estimating the number of via generation of the global routing path 22, calculating routing resource consumption information needed to connect the global routing path 22 with the multi-cut via, and referring to routing congestion to be calculated each of a plurality of rectangle areas to optimize a global routing path while aiming to uniform the routing congestion according to multi-cut via routing; a detailed routing means 14 for reading the global routing result and routing a detailed routing in the routing area by using the routing resource consumption information; and a multi-cut via replacement means 15 for reading the detailed routing result to replace a via for connecting the routing areas with the multi-cut via. PCOPYRIGHT: (C)2007,JPO&INPIT
机译:

要解决的问题:提供能够用于半导体集成电路的设计支持系统,用于半导体集成电路的设计方法,用于半导体集成电路的设计支持程序以及用于半导体集成电路的制造方法提高了从单切口通孔到多切口熊的替换率,并提高了半导体集成电路的可靠性和制造良率。解决方案:设计支持系统具有:全局路由装置13,用于将全局路由路径22分配给路由区域,估计全局路由路径22的通过的数量,计算用于将全局路由路径22与多路过孔连接,并参考要计算的多个矩形区域中的每个路由拥塞,以优化全局路由路径,同时旨在根据多路过孔路由来统一路由拥塞;详细路由装置14,用于读取全局路由结果,并通过路由资源消耗信息在路由区域中路由详细路由;以及多切口通孔替换装置15,用于读取详细的布线结果,以替换用于将布线区域与多切口通孔连接的通孔。

版权:(C)2007,日本特许厅&INPIT

著录项

  • 公开/公告号JP2007164536A

    专利类型

  • 公开/公告日2007-06-28

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;TOSHIBA MICROELECTRONICS CORP;

    申请/专利号JP20050360907

  • 发明设计人 UEDA TOSHIAKI;

    申请日2005-12-14

  • 分类号G06F17/50;H01L21/82;H01L21/822;H01L27/04;

  • 国家 JP

  • 入库时间 2022-08-21 21:13:11

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