首页> 外国专利> REDUCING DEFECT RATE DURING DEPOSITION OF A CHANNEL SEMICONDUCTOR ALLOY INTO AN IN SITU RECESSED ACTIVE REGION

REDUCING DEFECT RATE DURING DEPOSITION OF A CHANNEL SEMICONDUCTOR ALLOY INTO AN IN SITU RECESSED ACTIVE REGION

机译:在将通道半导体合金沉积到原位回退的活动区域中的过程中降低缺陷率

摘要

When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
机译:当基于阈值电压调节半导体合金来形成复杂的高k金属栅电极结构时,可以应用高效的原位工艺技术以便在专用有源区域中形成凹部并且用半导体合金重新填充该凹部。为了减少或避免在有源区域的凹陷期间与蚀刻有关的不规则性,可以控制在先前的处理期间,特别是在形成沟槽隔离区域期间的铝污染程度。

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